1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device including a cell string in which a plurality of memory cells are connected in series and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device is a kind of memory device which is capable of retaining stored data even when power supply is interrupted. Various nonvolatile memory devices such as a flash memory have been widely used.
FIG. 1 is a view illustrating a conventional nonvolatile memory device.
Referring to FIG. 1, a conventional nonvolatile memory device may include a tunnel dielectric layer 15, a plurality of gate patterns, first and second spacer dielectric layers 45 and 50, an interlayer dielectric layer 55, and contact plugs 60. The tunnel dielectric layer 15 is formed on a substrate 10. The plurality of gate patterns includes a floating gate electrode layer 20, a charge blocking layer 25, a passivation layer 30, a control gate electrode layer 35, and a gate hard mask layer 40, which are sequentially stacked on the tunnel dielectric layer 15. The first and second spacer dielectric layers 45 and 50 cover the plurality of gate patterns. The interlayer dielectric layer 55 is formed on the second spacer dielectric layer 50. The contact plugs 60 are formed to pass through the interlayer dielectric layer 55, the second spacer dielectric layer 50, and the tunnel dielectric layer 15. The contact plugs 60 are connected with the junction regions of the substrate 10.
In the conventional art, a chip size increases because a select line SL having a larger width than a word line WL occupies a substantially big area. In particular, in a case where word lines WL are formed by a spacer patterning technology (SPT), separate processes are required to form select lines SL with a width different from that of the word lines WL. Also, perturbation may occur by hot carrier injection (HCI) in the word lines WL which adjoin the select lines SL. Moreover, as a design rule decreases, it becomes gradually difficult to perform a process for partially removing the charge blocking layer 25 in the select lines SL.